SBIR-STTR Award

Rydal Research proposes to develop a high speed low-latency hardware-based implementation of multi-level security in a high-performance COTS protocol. The proposed method involves adding a sensitivity field to the Transport Layer header. Support for packet filtering will be added within the existing protocol specification. An additional error code will be developed to indicate errors and security violations in the filtering hardware. One or more real-time operating systems will be selected and the sensitivity level conveyed to the network interface via the operating system kernels. Fine-grain modeling and simulation will be used to determine the impact of the protocol modifications on system performance. An analysis will also be performed to determine the susceptibility and response of the protocol to intentional and unintentional security violations. All components needed to implement a complete system will be developed and demonstrated in Phase I in an FPGA-based prototype using Rydals reconfigurable computing platform and low-latency network switch. Flexible, robust, and easy-to-use software support will also be provided for system bring-up, maintenance, and troubleshooting. RapidIO will be used for the initial implementation but the techniques developed will be sufficiently flexible that they can be used with any other high-performance protocol.

Benefit:
The development of this system will benefit the Navy in a number of ways. First, the hardware-based approach will result in low latency needed for real-time performance. Second, the full network solution approach will provide the system implementer with all key building blocks ranging from cores to chips and subsystems needed to realize a complete system with low risk and cost. Third, the early development of useable FPGA-based products in Phase I will allow system integrators to use Phase I development boards to develop and evaluate prototype systems while the Phase II effort is progressing. Finally, the approach is extremely flexible, so that it may be used with other current or future high-performance network protocols.

Keywords:
High-performance networks, High-performance networks, Low-latency networks, Real-time Processing, Avionics, Multi-level Security, RapidIO

Rydal Research proposes to develop a low cost, high performance, shared memory multi-level secure data network capable of supporting data rates in the range of 10 Gbps per link. The network is based on a high-performance COTS networking protocol with appropriate extensions and enhancements to support multi-level security. The goal of the Phase II effort is to develop a complete set of building blocks needed to implement an MLS system in the military or commercial environment. To achieve this goal a number of key components will be developed in Phase II. First, a high performance low-power MLS switch ASIC will be designed and fabricated, based on the FPGA version developed under Phase I. This switch will work directly with MLS-enabled processors for an efficient low-chip-count solution. In addition, Rydal will continue to work through the relevant trade association to address Navy requirements in future protocol extensions and application notes and to ensure that these developments are compatible with the requirements of certifying agencies. To support non MLS-enabled processors Rydal will design and fabricate a generic MLS- endpoint bridge chip. This will be based on the bridge chip FPGA demonstrated in Phase I but with a PCI Express core replacing the existing bus interface. The development of this component will maximize flexibility and applicability.

Benefit:
The development of this system will benefit the Navy in a number of ways. First, the hardware-based approach will result in low latency needed for real-time performance. Second, the full network solution approach will provide the system implementer with all key building blocks ranging from cores to chips and subsystems needed to realize a complete system with low risk and cost. Third, the early development of useable FPGA-based products in Phase I will allow system integrators to use Phase I development boards to develop and evaluate prototype systems while the Phase II effort is progressing. Finally, the approach is extremely flexible, so that it may be used with other current or future high-performance network protocols.

Keywords: