SBIR-STTR Award

A New JVD System for Synthesizing Gate Dielectrics on SiC and GaN
Award last edited on: 3/27/2019

Sponsored Program
STTR
Awarding Agency
DOD : MDA
Total Award Amount
$60,000
Award Phase
1
Solicitation Topic Code
BMDO97T002
Principal Investigator
Guang-Ji Cui

Company Information

Jet Process Corporation (AKA: JPC~Schmitt Technology Associates)

57b Dodge Avenue
New Haven, CT 06473
   (203) 985-6000
   sales@jetprocess.com
   www.jetprocess.com

Research Institution

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Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
1997
Phase I Amount
$60,000
A number of wide bandgap semiconductors such as SiC, GaN, and diamond are being considered as the basis for the next generation of high-power and high-temperature electronics. SiC is the most promising materials for near term applications, since it shares many common features with Si processing, and the recent advances in the growth of both bulk SiC crystals and epitaxial layers have made high quality materials available for in-depth studies of their electrical properties. Many military and commercial systems today are requiring high temperature electronics to run smaller system size at high performance level. The Jet Process Corporation (JPC) has recently cooperated with Yale University on successful demonstration of high quality MNS capacitors, in which the silicon nitride layer is produced by the Jet Vapor Deposition Process (tm) (JVD(tm)) on silicon carbide substrates. Our MNS (Metal-SiN-SiC) capacitors show that the JVD nitride can form a high quality inversion layer on the SiC surface with low density of fix charge, low current density and high breakdown voltage. More recently, we are able to deposit high quality oxide dielectric layer at room temperature, which can reduce all the problems of high temperature thermal oxide. JVD(tm) is a patented, low cost, pollution free, and scaleable process. In Phase I, we will develop a JVD system which is suitable for depositing thin gate JVD oxide layer appropriate for MOS capacitors and MOSFETs on SiC. The new JVD system design will be experimentally demonstrated by making high quality MOS devices and integrated circuits with high reproducibility, reliability, and testability. In Phase II, we will work with government and industry labs to design and fabricate a prototype JVD system for MOSFETs on SiC wafers to demonstrate the feasibility. JPC will provide the JVD systems to the users to meet the need of the market for high temperature, high power electronics. Jet Vapor Deposition can produce high quality, high reliability gate dielectric layer deposition system for MOSFETs devices that are of great importance for applications in high-power high-temperature electronics for military and commercial applications.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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