Malicious modifications of hardware pose major concern in terms of reliable and trusted field operation of integrated circuits. To ensure security and trust of micro-chips, it is essential to develop efficient, low-cost techniques for detection of such tampering events. Conventional structural/functional testing, coverage metrics, and test generation approaches cannot be readily applied to identify these malicious changes, also referred to as Hardware Trojan horses. This SBIR Phase I project proposes to develop an automatic statistical test generation framework for combined functional and side-channel analysis based Trojan detection that provides very high confidence with respect to all possible Trojan forms and sizes. The effectiveness of the proposed test generation approach will be significantly enhanced by a low-cost, design-for-testability (DFT) approach that inserts test points at strategic design locations to significantly improve Trojan activation and observation probability. The tools for test generation and DFT can be seamlessly integrated with existing design flows for both application-specific integrated circuits (ASIC) as well as commercial-off-the-shelf (COTS) components. The project team has vast experience in hardware security and strong industry connections. The framework will be scalable to large industrial designs and will be evaluated with appropriate trust metrics.
