TriQuest Design Automation, Inc. and the University of Cincinnati propose to develop a preliminary design of a high level synthesis environment for complex digital systems. The proposed environment is multi-tiered and employs multiple point tools that cater to different abstraction levels. Based on a VHDL back-plane, this environment includes a high level synthesis tool, a state machine complier, a data path compiler, and a logic synthesis tool. It also includes a VHDL simulator for design validation. All the tools in the environment will be tightly integrated; this will result in accurate results and less iteration in the design process. Constraints will be propagated to downstream tools and synthesis results will be back-annotated in the upstream tools. Realistic design constraints such as area, power, delay, etc. will be handled.
Keywords: CAD EDA VHDL WAVES ESDA HIGH LEVEL SYNTHESIS RTL SYNTHESIS LOGIC SYNTHESIS
