The proposed Phase one Project goal is to design and simulate a down converter chip utilizing SiGe that provides pre-amplification, mixing and a flexible scheme of local oscillators to allow any 3 GHz segment of the frequency range between 3 & 40 GHz to be converted to dc-3 GHz for processing with a standard SOCOM 3 GHz receiver. The system architecture utilizes a minimal set of microwave oscillators from previous Centellax designs which are multiplied, divided and switched in a unique manner to provide the required performance and excellent SWaP. The use of 120 GHz Ft BiCMOS SiGe technology provides many advantages. Power consumption is low and the chip size is minimized. Reliability of the Silicon process is well understood and documented, better than GaAs and much better than InP. The process produces 8 inch wafers which makes costs low relative to the other technologies which use 4 or 6 inch wafers. SiGe has become more and more attractive for integrating high frequency subsystems as the Ft has increased in the last three years. Once feasibility is demonstrated in Phase one, specific designs matched to antenna configurations and specific radar requirements will be explored in Phase two.
