We propose a circuit design approach to enhance the tamper resistance against Focused Ion Beam (FIB) probing. Our approach is to break SINGLE clock network into MULTIPLE clock domains with the identical frequencies and phases. In the proposed clock generators design, the clock frequency for all domains will be kept within a small variation range. Therefore, FIB probing operation needs to keep up with the chip normal operation speed. However, the most advanced probe will increase the loading on the targeting nodes by at least one order of magnitude; the probed nodes will switch much slower than their normal operation speed. Thus a slower clock signal is required in order to get valid data stream from the probing nodes. Since the proposed clocking strategy will not allow clock slow down, the chip under probing can not function properly. The first order estimation shows that the difficulty to overcome this clock strategy increases exponentially with the number of the clock domain increasing. In contrast, the area/power penalty increases linearly with the number of clock domain increasing.
Keywords: DELAYED PHASE LOCKED LOOP, FOCUSED ION BEAM, ANTI-TAMPER (AT), REVERSE ENGINEERING
