SBIR-STTR Award

SystemVSIPL: Optimized Object Oriented Software Technology for Heterogeneous Computing
Award last edited on: 1/22/2007

Sponsored Program
SBIR
Awarding Agency
DOD : OSD
Total Award Amount
$849,999
Award Phase
2
Solicitation Topic Code
OSD03-022
Principal Investigator
Henk Spaanenburg

Company Information

Pentum Group Inc

44790 South Grimmer Boulevard
Fremont, CA 94538
   (408) 850-8192
   contactus@pentum.com
   www.pentum.com
Location: Single
Congr. District: 17
County: Alameda

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2004
Phase I Amount
$99,999
Pentum Group, Inc. proposes to implement SystemVSIPL by writing the VSIPL/VSIPL++ libraries and templates in the SystemC system development language. SystemC has been developed for complex electronic and real-time systems design, implementation, and verification. As an extension of C++, SystemC has all the benefits of Object-Oriented programming for efficient software development productivity, while its key features to support event synchronization and parallelism allow for the creation of very efficient and high performance parallel applications. SystemVSIPL will result in better optimizations and greater efficiency for modern multi-threaded COTS processors and complex heterogeneous systems. Since SystemC is a also used commercially for high-level firmware and hardware design, a SystemC approach will result in tighter integration across the whole design space from chip to software application. Most of all, SystemVSIPL should result in code that meets the needs for real-time response.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2005
Phase II Amount
$750,000
Pentum Group, Inc. (PGI) proposes development of SystemVSIPL to extend VSIPL and VSIPL++ to heterogeneous embedded processing systems. The implementation of SystemVSIPL in the SystemC language is ideal for the exacting and varied synchronization and data communication problems characteristic of parallel real-time embedded applications. SystemVSIPL will enable exciting new architectures, programs and most importantly will provide a framework for simulation, validation and verification as systems are ported and developed. SystemVSIPL will be a “Parallel VSIPL++” oriented to the particular needs of whole system design. What it all comes down to is the need to map algorithms and concepts into hardware in a manner that is efficient, acceptable and cost effective. This proposal specifically addresses the co-design and development of heterogeneous high performance embedded systems including FPGAs, as well as verification of subsequent software-transparent technology upgrades.