SBIR-STTR Award

The CipherProcessor architecture demonstrates reconfigurable opcodes unique to a specific processor or dynamically to a parallel environment and defined uniquely at compile time. Starting from a base of reconfigurable knowledge, Accord Solutions Inc will develop a reference design and demonstrate its viability. It incorporates an effective mechanism for delivery of compiled unique opcode binaries from development centers, with operation in standalone, multiuser and parallel modes. Accord will produce specification and performance projections from the CipherProcessor reference design, targeting advanced reconfigurable FPGAs, matrix driven array processors or System-on-Chip VLIW processors. A Cipherprocessor environment with a complete Fortran/ C++/ C path will be specified. The cost of compromise of the DoD's HPCMP National challenge software may be the cost of war, because application of this technology by enemies could lead to political instability. Less a threat but economically important is commercial software piracy. Protection of critical computational technology areas(CTAs) is thus vital. Cipherprocessor is a reference design that enables our embedded supercomputer products through software protection. In addition, licensing is planned to major processor chip manufacturers

Based on the hidden, unique opcode invention made and demonstrated in Phase I and its integration with CyberDog Communications Inc Object Level Firewall(OLF) authentication, key management and encryption technology, Accord Solutions Inc proposes to prototype the Reconfigurable Architecture for Software Protection (RASP) System. The RASP System provides an extremely strong level of cryptographic protection from quantum and supercomputer brute force attacks, preventing compromise of high value HPC binary executables through reverse engineering. In addition, there is low impact on HPC software development, with minimal impact on typical HPC working sets, with slight latency increases for disk IO and interprocessor communication. The RASP system uniquely distributes a single binary executable to each processor authenticated to execute it. Authentication by the OLF provides assurance that access is made only by validated processors. Data input and output is likewise protected, but with different keys, ensuring that no user can access the binary executable for reverse engineering exploitation. Parallel processing uses a different set of RASP keys to protect interprocessor communication. The Phase II effort produces three prototypes: purely software, FPGA accelerated software and a printed circuit board. Each of these prototypes will be demonstrated (single, parallel and staged) using an instrumented test bed.

Keywords:
SOFTWARE PROTECTION, QUANTUM BRUTE FORCE SECURITY, ONE TIME PAD IMPROVEMENT, HIDDEN UNIQUE OPCODE, RECONFIGURABLE ARCHITECURE FOR SOFTWARE PROTECTION