This Small Business Innovation Research (SBIR) Phase I project proposes to develop a novel, electrostatic based metrology solution that has the potential of being developed into a rapid and quantitative test of interfacial adhesion for the semiconductor industry. The portion of a semiconductor device that carries logic signals between the transistors on a chip is commonly known as the Back-End-of-the-Line (BEOL). The BEOL typically consists of, among other components, current carrying metal lines surrounded by an insulating or low-dielectric constant (low-k) material. To keep increasing chip performance at the current pace, it will be necessary to replace the current dense insulators with a porous low-k material. Interface adhesion between porous low-k and the various other layers in the BEOL is known to be poor and extremely problematic during integration. The semiconductor industry faces a significant barrier to further progress, because a rapid and quantifiable test to assess interfacial adhesion does not currently exist. The principle of the technique is to use a normal tensile force created by an electrostatic field to delaminate thin films from their underlying layers. This is a unique undertaking with regards to adhesion testing and reflects a revolutionary shift in how adhesion tests will be conducted if successful. The economic benefit to the industry will be achieved by reducing the time to market and improving yield. If interfacial adhesion can be monitored rapidly and quantifiably, the effects of varying process parameters (deposition, etch, pre-treatments) on film-adhesion can be quantified in a greatly shortened time reducing the length of the process development and R&D phase. This would lead to shorter times to market, increased productivity, and may increase market share for early adopters of the technology in the US.
