This Small Business Innovation Research Phase I project derives, designs, evaluates, tests, and produces forward error correcting codec chip sets. By introducing a modified BCH code into the Internet TCP structure without changing the TCP/IP format, it is feasible to achieve simultaneously: 95% throughput enhancement, 4-order bit error rate improvement, 80% effective delay reduction, transmission speed up to 10 Gbps, and channel utilization approaches unity Erlang. Two decoding algorithms are to be investigated for large quantity production in terms of speed, correcting capability beyond theoretical limit, and complexity. Computer programs will be generated and simulations will be performed. Next, a Field Programmable Gate Array (FPGA) device will be selected, designed, evaluated, 'burned', and tested before VLSI implementation. The result meets the international standards for Asynchronous Transfer Mode, Internet, and satellite communications.
The proposed product is simple, low cost, and in need. The applications range from ATM, Internet, and satellite communications. The market share of ATMco for Internet alone is estimated at $750 Million over more than 5 years for a device to be priced at $25 per unit.
