This Small Business Innovation Research Phase I project will develop a novel, compact, low-cost, and single chip adaptive neuroprocessor. This bit-serial based digital CMOS VLSI electronic neural network device will combine on-chip integration of a fully reconfigurable feedforward/time-lagged recurrent neuroprocessor with a backpropagation weight training module. Specifically, the technical objective of this research is to develop a neuroprocessor chip suitable for direct insertion into Ford's advanced concept vehicles. In operation, this stand-alone electronic neural network will act as a co-processor to the engine computer's (EEC) central processing unit (CPU). The neuroprocessor will be software programmable, enabling it to execute multiple different neural network applications on-the-fly; be capable of event rate computational throughput (< 100 microseconds) per application; be of a single-chip design (neuroprocessor with on-chip weight training); and cost effective (< $20/chip). The importance of on-chip adaptation is to address the problems of fixed weight neural networks--namely that an applications synaptic weights (as optimized at the factory for a generic model) be allowed to tweak/self-calibrate themselves for optimal diagnostic and control performance on the vehicle in order to handle most accurately all conditions under which the particular system is deployed. This research is in direct collaboration with Ford Motor Company. The end product of this research and development is particularly relevant to all diagnostics and control applications in the automotive industry, in aerospace, as well as process control in the electronics commercial industry.
