SBIR-STTR Award

A 4 GHZ Multi-Chip System for High Resolution Analog-to-Digital Converters
Award last edited on: 3/14/02

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$50,000
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Juzer S Mogri

Company Information

MEI Research

4097 Chiltern Drive
Fremont, CA 94538
   (415) 656-9210
   N/A
   N/A
Location: Single
Congr. District: 17
County: Alameda

Phase I

Contract Number: 9060826
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1990
Phase I Amount
$50,000
Gigasample analog-to-digital converters (ADCS) are needed in many fields, from advanced information processing systems to scientific instrumentation used in high energy Physics experiments. As higher speed ADCs become available, signal capture functions which were only possible in the analog domain, now become possible to achieve in the digital domain, where more sophisticated (and far more accurate) signal processing functions may be applied. Gallium Arsenide (GaAs) technology promises a nearly tenfold increase in conversion rate, however, GaAs ADC development has been plagued with problems for which no near term solution is foreseen. The technique currently being investigated should hasten the realization of the promise of GaAs. At the same time, it can be applied to any other technology where there is a significant difference between the signal bandwidth and the current driving capability of the technology. A most promising case in point is the possibility of using this technique to realize low-power high resolution ADCs in submicron BICMOS applicable to high definition video technology (HDTV).The potential commercial application as described by the awardee: The importance of a "flash" ADC with multigigasamples/sec. conversion rate to the competitive position of the United States in the world market place cannot possibly be overestimated. ADCs are the pacing components in many advanced signal processing systems and in Scientific and Engineering Instrumentation. This technique may also be applicable to submicron BICMOS to develop lowpower, cost-efficient ADCs for high definition video displays (HDTV).

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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