Novati intends to leverage our existing Heterogeneous Integration expertise, along with 2.5 and 3D Direct Bond Interconnect (DBI) Technology, and broad semiconductor Process Technology developed by Novati and its predecessors in order to achieve a minimum of one million interconnects among a wafer stack of up to five 8-inch wafers of a minimum of three different substrate types (including one silicon). Final products will be demonstrated to meet the Navys DC testing requirements, and Novati offers RF testing as further validation of the performance and reliability of the interconnect technology as well as the ability to scale the manufacturing process while retaining the beneficial reduction in SWAP-C at a yield rate of 99% per the Navy guidelines. Test results will also validate that Novatis selected integration techniques do not impede or degrade device performance. Competing 3D processes require large area exclusions that require valuable die area and result in the disruption of the BEOL interconnect stack of at least one IC layer in a 3D IC. DBI allows for direct connections to be made between ICs as part of the bond process without disrupting and compromising the interconnect stack. With DBI, 3D IC cost is minimized by avoiding design exclusions in the interconnect stack and delivering a vertical interconnections between IC layers in a 3D IC that can scale with the process node.
Benefit: Reduction in SWAP-C represents an opportunity for the U.S. Navy to secure greater intelligence and operational/competitive advantage by improving and increasing chip functionality to a degree that allows for a wide range of custom defense applications. Such custom applications might include high-density memories and processor-memory integration for high performance computing applications, thermal imaging technologies, and advanced T/R modules and Active Electronically Scanned Arrays (AESAs) for radar, communication, EW and multifunction systems. Examples of current applications that might be drastically improved or optimized using Novatis 3D Interconnect Technology include night vision, persistent surveillance and security applications including airborne and satellite-based systems. Optimized performance with reduction in SWAP-C is evidenced in camera on a chip 0x9D architectures, where 3D integration is the key enabler with the image sensor, read-out circuitry and signal processing logic chips all vertically integrated using vertical wiring between the substrates. The ability to achieve this at wafer-scale rather than die-to-die also has an enormous impact on cost with further savings at scale.
Keywords: wafer bonding, wafer bonding, DBI - Direct Bond Interconnect, Heterogeneous Integration, 3D interconnect, TSV - Thru Silicon Via
