SBIR-STTR Award

The primary objective of this Phase I project is to determine the extent of the significant reduction in power consumption of integrated circuits which may be achieved by utilizing a novel side gate FET technology. The new FET technology promises to eliminate the Narrow Channel Effect (NCE) which is one of the primary factors limiting the minimum power consumption of integrated circuits, By eliminating the NCE, we will be able to scale the device size dramatically and reduce the power, speed, circuit design, processing, and manufacturability of the new FET technology for both digital and analog circuits. In particular, we will extract device parameter form the ultra-low power FETs fabricated at UVa, develop device models, incorporate these models into a new SPICE package (AIM-Spice), simulate different logic families including DCFL and SCFL, and compare the predicted performance with the standard DCFL and SCFL logic. We will also analyze the gate current leakage and subthreshold slope as the primary factors limiting the noise margins as low power supplies, establish the minimum required bias voltage for reliable operation, and analyze the factors determining the threshold voltage changes from device to device as well as other factors which may limit the yield and integration scale.

Keywords:
Low Power Electronics Microwave Narrow Channel Effect Manufacturing

The primary objectives of the Phase II work are to build upon the achievements of Phase I and to demonstrate low power-delay 2-D MESFET DCFLcircuit elements for wireless applications. The Phase I work demonstrated the 2-D MESFET DCFL inverter having a lower power-delay product than CMOS, SOI, GaAs MESFET, or any other FET technology, excellent noise margin at low supply voltage, greater functionality due to the novel geometry and a simple fabrication technology compatible with high speed analog FETs. In addition, deleterious narrow and short channel effects are greatly reduced in sub-micron devices. The Phase II work will continue to develop the 2-D MESFET device technology as well as increase the DCFL circuit complexity. Our Phase II objectives therefore include the demonstration of simple DCFL circuits including inverters,inverter chains, NOR and NAND logic gates as well as ring oscillators (to evaluate power-delay) and other logic circuits in order to demonstrate compact, ultra high speed, low power DCFL logic. These Phase II objectives should clearly demonstrate the promise of the 2-D MESFET technology for advanced, energy efficient electronics. Our Phase III effort will focus on increasing the scale of 2-D MESFET ICs and on demonstrating ultra low power application specific ICs for wireless communications products. The proposed technology should find applications in low power, high speed analog and digital dual use electronics such as battery powered personal communications systems, portable computers, solar powered surveillance and security systems, medical and space electronics, and many applications for which a significant power reduction is desired.

Keywords:
Low Power Electronics Microwave Narrow Channel Effect Manufacturing