The effects of negative voltage pulses (resulting from signal reflections) on the input signal pins of NMOS technology microcircuits are largely unknown. This phase I proposal explores the feasibility of an extensive test and evaluation program to determine the short-term and long-term effects on performance and reliability degradation. The programs will examine the effects of negative voltage pulse amplitude and duration, pulse rise/fall-times, and pulse repetition rates on NMOS dynamic ram microcircuit anticipated results include: 1) an accurate characterization of the effect of those parameters related to undershoot in NMOS microcircuits, and 2) preliminary work toward the design of an input structure which minimizes the susceptibility of NMOS devices to those effects. Based upon these results suggestions will be made for: minimizing the effects of undershoot in both existing circuits and systems; new designs for both military and commercial applications.
