SBIR-STTR Award

Highly Parallel, Fast Memory, Peripheral Access for RISC-V Many-Core Processors
Award last edited on: 1/23/2023

Sponsored Program
SBIR
Awarding Agency
NASA : GSFC
Total Award Amount
$924,705
Award Phase
2
Solicitation Topic Code
Z2.02
Principal Investigator
Chinh Le

Company Information

Lewiz Communications Inc

738 Charcot Avenue
San Jose, CA 95131
   (408) 432-6248
   info@lewiz.com
   www.lewiz.com
Location: Single
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: 80NSSC21C0237
Start Date: 5/13/2021    Completed: 11/19/2021
Phase I year
2021
Phase I Amount
$124,905
High performance computing system requires many-core processor with network-on-chip (NOC) interconnecting the cores. A major issue is the competition of the many cores for access to memory. Example of this can be seen in GPU designs. In addition, systems traveled to remote planets perform large data analytic, image processing, autonomous applications remotely. These are not suitable for general cache-based designs, causing cache miss often and thrashing performance. NOC designed for cache system are also not suitable for large data transfers from accelerators of such applications and high-speed peripherals (PCI-express, Ethernet) to memory. Space travel further requiring fault tolerant (FT), ECC capabilities. Current solutions for RISC-V do not address all of these issues. 2021 NASA SBIR topic Z2.02 calls for “a fault-tolerant RISC-V processor IP core … that is augmented to provide data parallelism, which is needed to accelerate image processing and science data processing.” LeWiz developed a 64-bit FT RISC-V processor core in a previous NASA SBIR Phase 1 for many-core CPU architecture. This work will enhance its NOC design and implements new, highly parallelized NOC based FT memory controller supporting multi-banks, high bandwidth memory where large number of independent access channels are available, more suitable for large data processing. This augmentation will provide the best, highly parallelized data access for many-core processor using state-of-the-art DRAM technology meeting NASA topic requirements Potential NASA Applications (Limit 1500 characters, approximately 150 words): space/deep-space travel, exploration. Results can be used on spacecrafts, satellites, orbiting stations, robots, autonomous systems in space, Moon, remote planets. Applications include flight control, navigation, instruments, communication, high performance computing systems. Aircrafts also benefit from the technology created. Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words): Commercial spacecrafts, satellites, orbiting stations, missiles, weapon systems, communication systems, high performance computing for Department of Defense, Missile Defense Agency, Navy, Air Force, and commercial companies (Boeing, SpaceX, Lockheed, etc.) are potential applications of the technology Duration: 6

Phase II

Contract Number: 80NSSC22CA137
Start Date: 4/26/2022    Completed: 4/25/2024
Phase II year
2022
Phase II Amount
$799,800
LeWiz research from NASA Phase 1 I-Corps program showed very strong interest in LeWiz solutions from NASA telescope team, DoD lab and commercial storage customers with potential for immediate revenue. Previously, LeWiz developed fault-tolerant (FT) 1) high performance network-on-chip bus (NOC) for multi-channel access supporting High Bandwidth Memory controller and/or high speed peripherals, and 2) 64-bit, 6-stage RISC-V CPU core with NOC interface capable up to 500K cores in a system. This Phase 2 proposed to further develop the Phase 1 solutions to meet the immediate customer requirements and productize the solutions for infusion into NASA and commercial customer products. 2 subsystems would be developed i) spectrometer memory/peripheral subsystem with highly parallelized access channels supporting DDR4 memory, 100Gbps Ethernet, multiple digital-to-analog converters, ii) RISC-V processor with enhanced NOC router integrated to the highly parallel NOC/HBM controller. The solution would also meet NASA SBIR Z2.02 Topic requirements for "A fault-tolerant RISC-V processor IP core ... that is augmented to provide data parallelism, which is needed to accelerate image processing and science data processing." and enabling future development of accelerators and co-processors for many-core high-performance processing architecture advancing state of the art FT processors for space flights and autonomous applications. No other known solution is as advanced as the proposed for space applications. The project will be carried out over 2 years in the US. Potential NASA Applications (Limit 1500 characters, approximately 150 words): NASA applications include flight control, landing control, instrumentations, payloads, sensors, navigation systems, networking, scientific processing, image processing, communication sub-systems for satellites, space stations, vehicles, space habitats. Very strong interest from NASA Microwave Kinetic Inductance Detector Team for space telescope applications in spectrometer (Origin Space Telescope) and RF-submillimeter (SELFI) programs Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words): Non-NASA applications include flight/landing control, instrumentations, payloads, sensors, navigation, networking, image processing, communication subsystems for satellites, space stations, air/space/ground/sea vehicles, weapon systems. Strong interest from Tier-1 network storage vendor. Contract negotiation in progress for custom development Strong interest from DoD research lab for space systems Duration: 24