SBIR-STTR Award

Adsantec will develop a single package Application Specific Integrated Circuit, capable surviving and maintaining performance in high radiation environments (> 1 Mrad), including enhanced low dose rate sensitivity. The DAC will have a sampling rate greater than 1 Gb/s with effective number of bits >6. The design will be based on the company’s proprietary reconfigurable DAC architecture, which incorporates a patented pseudo straight forward synchronization algorithm (PSFS) and a patented rad hard clock recovery/Phase Lock Loop Scheme. The proposed PSFS will be implemented inside developed ASIC minimizing overhead during data transmission. In this design, ADSANTEC will employ proven SiGe bipolar transistor-based circuit blocks based on our hard-by-design methodology. The use of ADSANTEC’s space qualified ASIC packaging will enable fabrication and test of a TRL 7 or higher ASIC prototype at the end of Phase II. Potential NASA Applications (Limit 1500 characters, approximately 150 words) The digitizer will greatly support the performance of NASA’s SLPS and Martian programs and can be also used for wireless communications. Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words) The developed ASIC can be used in variety of US Air force space missions, wireless communications and measurement instrumentations.

Adsantec will design and fabricate a Digital-to-Analog Converter (DAC) as a single-package Application Specific Integrated Circuit, (ASIC) capable of surviving and maintaining performance in high radiation environments (> 1 Mrad), including enhanced low dose rate sensitivity. The DAC will have a sampling rate greater than 2 Gb/s with effective number of bits >10. The design will be based on the company’s proprietary reconfigurable DAC architecture, which incorporates a patented Pseudo Straight Forward Synchronization algorithm (PSFS), a patented rad-hard Clock Recovery scheme and a proprietary rad hard Serial Peripheral Interface. It will allow direct interfacing with a variety of Field Programmable Gate Arrays (FPGA) used by NASA and other space customers. The robust DAC architecture will incorporate both serial and parallel FPGA to DAC interconnect The proposed PSFS will be implemented inside the developed ASIC minimizing overhead during data transmission. In this design, ADSANTEC will employ proven SiGe bipolar transistor-based circuit blocks based on our rad hard-by-design methodology. The use of ADSANTEC’s space qualified ASIC packaging will enable fabrication and test of the DAC with TRL 7 or higher ASIC prototype at the end of Phase II. Potential NASA Applications (Limit 1500 characters, approximately 150 words): The successful accomplishment of this project resulted in the development of several versions of the DAC ASIC that can support multiple NASA space missions including CLPS, Mars Sample Return, Asteroid/NEO Sounder, and Ocean World Sounder. In particular, a significant improvement can be achieved in the landing radar sensor. The parts will be also beneficial for such NASA Earth programs as ACCP, SDC, and STV. Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words): The developed DAC can easily be integrated into high performance measurement systems intended for the next generation of Earth System Science measurements of its atmosphere and surface as well as variety of Air Force space missions Duration: 24