SBIR-STTR Award

pMTJ STT-MRAM based Chiplets for Neuromorphic Computing
Award last edited on: 1/20/2024

Sponsored Program
SBIR
Awarding Agency
NASA : ARC
Total Award Amount
$124,581
Award Phase
1
Solicitation Topic Code
H6.22
Principal Investigator
Rajiv Ranjan

Company Information

Avalanche Technology Inc

3540 West Warren Avenue
Fremont, CA 94538
Location: Single
Congr. District: 17
County: Alameda

Phase I

Contract Number: 80NSSC19C0309
Start Date: 8/19/2019    Completed: 2/18/2020
Phase I year
2019
Phase I Amount
$124,581
Avalanche Technology will offer MRAM chiplets based on its pMTJ STT-MRAM technology. Avalanche’s MRAM chiplets use Generic MRAM Interface (GMI). The GMI is modeled on the widely-used HBM interface and is optimized for memory accesses. In addition to the memory interface, MRAM chiplets need a second interface to communicate with the rest of the chiplets in a multi-chiplet system. For example, Intel’s Advanced Interface Bus (AIB) protocol is in the forefront for direct chiplet-to-chiplet communication for DARPA’s CHIPS (Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies) program. To be used in AIB-based systems, Avalanche’s MRAM chiplet will have an AIB interface and an adapter from the AIB to the HBM interface for the MRAM array. Potential NASA Applications (Limit 1500 characters, approximately 150 words) Demonstration of Compute in memory (CIM) for Neuromorphic applications utilizing proven Radiation Hardened STT-MRAM products from Avalanche Technology for Harsh environments. Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words) Deep learning and Artificial Intelligence in a wide variety of tasks such as computer vision, image and speech recognition, machine translation, robotics and medical image processing.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
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