SBIR-STTR Award

VORAGO Technologies will create a rad-hard I/O Expansion Chip for next generation spaceflight processor devices, including the High-Performance Spaceflight Computing (HPSC) Chiplet. The I/O Expansion chip will have multiple high-speed interfaces so that it can interface with a space processor and support high speed communications. It will also have programmable-voltage-level GPIO to support both non-differential communications protocols and general I/O expansion. The I/O expansion chip will provide dedicated hardware on the IC to support each of the communications protocols. The I/O expansion chip will also include an appropriate amount of memory and a multi-channel Direct Memory Access controller system to support simultaneous high-speed communications. To optimize power consumption, multiple PLL sources will be available on-chip to provide the appropriate clock generation for the on-chip communications controllers. An ARM® A5 processor core will be included on the I/O Expansion Chip so that it can be used autonomously from the spaceflight processor device. This feature is expected to give the system designer good options for system level power saving modes as well as more system fault management capabilities. The I/O Expansion chip will be implemented using VORAGO Technologies proven radiation-hardening HARDSIL® technology. HARDSIL technology will make the I/O Expansion chip immune from latch-up. Potential NASA Applications This device will be an ideal companion part for next generation spaceflight processor devices, including the High-Performance Spaceflight Computing (HPSC) Chiplet. Programming the device and supporting software will be straightforward as it is based on an existing widely used ARM Cortex architecture. Possible applications of the device would be: - I/O Expander for processors or FPGAs, - Multi-communications interface / hub for processors or FPGAs, - Network bridge for processors or FPGAs, - Standalone A5 class processor with multiple communications interfaces, - Redundant processor system for implementing additional system-level lower power modes, - Redundant processor system for implementing failsafe strategy Potential Non-NASA Applications Based on our experience marketing ARM Cortex-M based microcontrollers to the space market, we have determined that is a demand for a device like the I/O Expander Chip for the types of applications that are stated in section 10.1. This device, implemented in CMOS and radiation-hardened by HARDSIL would be an ideal companion chip to next generation spaceflight processors as well as a cost-effective alternative to solutions such as some expensive FPGAs and SPARC-based products.

VORAGO Technologies has produced an IC definition and architecture for a rad-hard I/O Expansion chip that is capable of interfacing to next generation spaceflight processor devices including the High-Performance Spaceflight Computing (HPSC) chiplet. We have gathered the best available knowledge of HPSC use-cases to conceptualize and articulate the requirements for an I/O Expansion Chip, creating an architecture for an optimized and robust IC that can be implemented to meet the requirements of next generation NASA space electronics systems. In addition to providing a perfect companion IC to the HPSC in next generation systems architectures, the I/O Expansion Chip can facilitate the use of the HPSC with legacy systems (such as those that include MIL-STD-1553 communications). Support of legacy systems is a practical requirement for the next decade. The I/O Expansion Chip will allow the HPSC to interface with legacy systems as well as next generation systems. We most recently added USB 3.0 to the definition to support camera interfaces that are being considered / selected for Orion and SPLICE programs at NASA Johnson Space Center. VORAGO Technologies would like to commercialize the I/O Expansion Chip product and target sales to NASA and non-NASA commercial aerospace customers. Making the product commercially successful outside of NASA applications will increase sales volume and establish a more robust supply chain for the product. In phase II, we propose to create a detailed IC specification, acquire the main IP blocks and create a hardware prototype system of the I/O Chip using the Synopsys HAPS80 prototyping system. This approach is consistent with that taken for the HPSC chiplet development process. Potential NASA Applications (Limit 1500 characters, approximately 150 words) The I/O Expansion Chip will be suitable for use in spacecraft, and cyber-physical/robotics or autonomous systems in space radiation environments. Everywhere that an HPSC device can be used, it is likely that one or more I/O Expansion Chips can be used. Such applications include: Vision-based algorithms with real-time requirements (e.g. landing with hazard avoidance), Model-based reasoning techniques for autonomy (e.g. Mars rover mission planning), High rate instrument data processing (e.g. high-resolution satellite image processing) Potential Non-NASA Applications (Limit 1500 characters, approximately 150 words) I/O Expansion for processors & FPGAs, Multi-comms interface & hub for processors & FPGAs, Network bridge for processors/FPGAs, Standalone A5 class processor with multiple comms interfaces, Redundant processor system for implementing system-level low power modes, Redundant processor system for implementing failsafe, Interface to cameras on Orion and SPLICE programs that use USB 3.0 camera interface