SBIR-STTR Award

Speaker Driver and Wireless Transciever ASIC
Award last edited on: 2/20/2018

Sponsored Program
SBIR
Awarding Agency
NASA : JSC
Total Award Amount
$124,888
Award Phase
1
Solicitation Topic Code
H4.03
Principal Investigator
Tracy Johancsik

Company Information

Silicon Technologies Inc

4568 South Highland Drive Suite 300
Salt Lake City, UT 84117
Location: Single
Congr. District: 03
County: Salt Lake

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2016
Phase I Amount
$124,888
A robust and reliable wireless communication system capable of surviving the harshness and radiation of space is required for future space missions. Current EVA (Extra Vehicular Activity) communications systems are out dated and in need of an overhaul. Silicon Technologies Inc. (STI) proposes to design a wireless communication ASIC that will include audio DACs, ADCs, and a Dual-band WLAN as well as speaker drivers for a complete communication solution. To minimize design and layout time, STI shall use its ADONIS Rad Hard by Design Analog Cell Library (RADL). RADL contains the basic components required for the design of the ASIC including radiation hardened by design operational amplifiers, voltage references, analog transistors, resistors and capacitors. STI has developed a revolutionary new design tool, ADONIS, which will be used for this ASIC design. One of the key benefits of using STI's ADONIS technology is that it provides NASA Rad Hard technology that is portable to new processes and will extend the potential life of the program by ensuring that the design can be manufactured in a new fab if the existing fab closes. Additionally, ADONIS can do this at a lower cost with reduced risk compared to existing design technologies. In Phase II, STI shall take the feasibility design in Phase I, build a prototype ASIC, and test the silicon electrically before and after radiation exposure. Other advantages of the patented ADONIS design technology are: (1)Consistent cell structures with Rad Hard design, (2)Reduced mask costs by 80% using conventional techniques, (3)Repeatable structures which control leakage, (4)Interactions between cells are known at design time, (5)Faster design cycle resulting in a savings of more than 2x standard design time, (6)Portability between different CMOS processes (7)Noise and IR reduction due to a proprietary power and ground mesh, (8)1D approach, and (9)Compatible with future Ebeam Direct Write Technology when it is commercialized.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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