SBIR-STTR Award

Radiation Hard Electronics for Advanced Communication Systems
Award last edited on: 1/14/2015

Sponsored Program
SBIR
Awarding Agency
NASA : GRC
Total Award Amount
$849,881
Award Phase
2
Solicitation Topic Code
-----

Principal Investigator
Sterling Whitaker

Company Information

ICS LLC (AKA: Integrated Circuit Solutions)

721 S Lochsa Street Suite 8
Post Falls, ID 83854
   (208) 315-2877
   N/A
   www.ics4chips.com
Location: Single
Congr. District: 01
County: Kootenai

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2011
Phase I Amount
$99,954
Advanced reconfigurable/reprogrammable communication systems will require use of commercial sub 100 nm electronics. Legacy radiation tolerant circuits fail to provide Single Event Upset (SEU) immunity at speeds greater than 500 MHz. New base level logic circuits are needed to provide SEU immunity for high speed circuits afforded by sub 100 nm technology. A completely new circuit and system approach called Self Recovery Logic is proposed for development herein which is able to function at the full speed afforded by the fabrication process and able to tolerate SEU impacts not possible with legacy circuits. Moreover, a truly fault tolerant system is proposed which is projected to replace Triple Modular Redundancy as the on-chip means for fault tolerance. With the proposed building blocks in place, advanced reconfigurable and reprogrammable high speed devices can be implemented. A multiprocessor with advanced error correction and data compression capability is proposed for future development.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2012
Phase II Amount
$749,927
Advanced reconfigurable/reprogrammable communication systems will require use of commercial sub 100 nm electronics. Legacy radiation tolerant circuits fail to provide Single Event Upset (SEU) immunity at speeds greater than 500 MHz. New base level logic circuits have been demonstrated in Phase I that provide SEU immunity for sub 100 nm high speed circuits. A completely new circuit and system approach called Self Recovery Logic (SRL) is proposed for development herein which is able to function at the full speed afforded by the fabrication process and able to tolerate SEU impacts not possible with legacy circuits. Moreover, a truly fault tolerant system is projected to replace Triple Modular Redundancy (TMR) as the on-chip means for fault tolerance. With the proposed building blocks in place, advanced reconfigurable and reprogrammable high speed devices can be implemented. The proposed work herein creates a robust test circuit for fabrication and radiation testing to prove conclusively that SRL is a superior technology and then to create an SRL synthesis library that can be used with commercial synthesis tools to create advanced communication systems.