The EVA digital radio imposes tight constraints on power consumption, latency, throughput, form factor, reconfigurability, single event upset and fault tolerance, and security. This requires a complete rethink on the digital radio architecture. We propose such an architecture called CHANDRA that exploits a cycle-by-cycle reconfigurable FPGA that is based on state-of-the-art double-gate CMOS and nano RAM technology. In order to make the FPGA, and hence CHANDRA, ultra-low power, we will investigate various FinFET implementations, 3D architectures, and dynamic power/QoS management techniques. This will be aided by the presence of nano RAMs, such as NRAMS, MRAMs, PCMs and embedded DRAMS, for on-chip configuration and data storage. The FPGA will be implemented with the currently used chip fabrication technology: photo-lithography. We propose to map novel non-GPS relative location-aware algorithm based on a hybrid distributed localization concept, multimode protocol functioning for voice (VoIP), video, data transmission, and run digital radio applications starting from the simulation level to relevant environment demonstration towards providing the miniaturized EVA Digital Radio.
