SBIR-STTR Award

Flight Lossless Data Compression Electronics
Award last edited on: 1/14/2021

Sponsored Program
STTR
Awarding Agency
NASA : GSFC
Total Award Amount
$698,428
Award Phase
2
Solicitation Topic Code
T4.01
Principal Investigator
Joseph J Feeley

Company Information

ICS LLC (AKA: Integrated Circuit Solutions)

721 S Lochsa Street Suite 8
Post Falls, ID 83854
   (208) 315-2877
   N/A
   www.ics4chips.com

Research Institution

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Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2006
Phase I Amount
$99,243
The proposed work seeks to drastically increase the capability of the lossless data compression technology embedded in the currently used flight part known as USES (Universal Source Encoder for Space). USES met the CCSDS 121-0-B 1 recommendation. New advances to the lossless data compression electronic technology which advances the current flight electronics device: * Increase quantization levels to 32 bits; the current device supports only 15 bits. * Support multi-frequency simultaneous inputs, at least three to represent color inputs. * Increase speed from 20 MSamples/sec to 200 M Samples/sec * Realize in a radiation tolerant 0.25 micron CMOS process

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2009
Phase II Amount
$599,185
There is a valid scientific data paradigm where no loss of data can be tolerated. However, transmission of raw data requires unacceptable bandwidth and storage resources such that the net data received is uncomfortably low. Lossless data compression can be used to preserve all data with no information loss and also help meet bandwidth and storage constraints. The current Universal Source Encoder of Space (USES) has been meeting many lossless compression needs for a decade. However, USES is not able to successfully address higher speed instruments, beyond 20 MSamples/sec, or function at quantization levels higher than 15 bits. The proposed work provides a new solution and presents a lossless data solution that should be valid for at least a decade or more. A radiation tolerant high performance (100M Samples/second) 32-bit lossless custom processor will be delivered in the proposed work which meets the CCSDS 121-0-B 1 recommendation. The processor will be implemented in a radiation tolerant 0.25 micron CMOS process which realizes a proven algorithm developed at GSFC and implemented in a 15-bit version 10 years ago. The new compressor is 5 times faster and has twice the input quantization range, suitable for modern spacecraft requirements. The net-list (design) of the processor can be used to synthesize a future 200 Msamples/sec plus data rates when a sub-100 nm radiation tolerant fabrication process is available.