This Small Business Innovative Research Phase I project proposes to develop a novel high performance hardware implementation of the stereo vision algorithm developed at JPL by Larry Matthies and co-workers in the Machine Vision Group. While there have been a number of reported hardware implementation reported to-date, our implementation will be the first such implementation to achieve all four design objectives, these being: real-time capability (1 to 30 Hz frame rate); high-resolution images (up to 640x480 raw stereo images pairs); ultra-low power consumption (300 mW or less); design compactness (single chip implementation) Our architecture is based on a novel hardware design that is highly parallel, fully pipelined, computationally efficient, and can be implemented on radiation hardened field programmable gate arrays (FPGA) or ASICs, and is particularly well suited for robust, real-time and high-resolution depth-of-field computations as required by the next generation of on-board robotic navigation systems for planetary exploration. POTENTIAL COMMERCIAL APPLICATIONS It is widely accepted that stereo vision will play an important role in the automotive industry's plans for 'intelligent' highways and 'smart' cars. Driven by the ever increasing vehicular congestion and consumer demand for safer vehicles, there is a growing consensus that collision avoidance systems are only a short way off. For robustness, these systems will be based on fusing stereo vision and laser range finder modalities to create a safe envelope around the vehicle, allowing the vehicle to safely and autonomously extricate itself from a potential crash. As such, there will soon exist a mass market for a high resolution, extremely fast, and cost effective stereo vision systems in the automotive industry.
