The PMEL (Processor Memory Element)architecture is a means of using internal parallelism in a chip design to perform DSP or RISC processing. The internal processing in the chip under a single program counter permits an 800% increase in performance. Although a VLIW instruction stream is used, this is NOT a classical VLIW design. The unique PMEL structure using on chip "intelligent memory" eliminates a von Neumann bottleneck in the data store cycle. This includes the path from the ALU data execution to the storage in register memory. This is accomplished by an efficient bussing scheme which permits a one cycle fetch, execute, and save. If a 250 MHZ clock is used to process instructions, the architecture outputs operations at 2000 MIPS, so that there is no additional power dissipation penalty associated with the significant performance increase. The increase in performance without severe power penalties offers NASA a computational device with potential for a variety of agency needs.
