SBIR-STTR Award

Verified VHDL Synthesizable Cores
Award last edited on: 3/11/02

Sponsored Program
SBIR
Awarding Agency
NASA : LaRC
Total Award Amount
$657,347
Award Phase
2
Solicitation Topic Code
-----

Principal Investigator
Bhaskar Bose

Company Information

Derivation Systems Inc

5963 La Place Court Suite 208
Carlsbad, CA 92008
   (760) 431-1400
   bose@derivation.com
   www.derivation.com
Location: Single
Congr. District: 49
County: San Diego

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1996
Phase I Amount
$69,846
The development of verified reusable hardware specification components, manifest as synthesizable VHDL cores, represents a key technology that will enable engineering discipline to manage design complexity. The specific innovation we propose is the development of verified, synthesizable VHDL cores that include all the features, documentation, and support necessary to insure integration with customer designs with the high degree of reliability provided by the application of formal methods. The innovation is relevant to NASA as (i) an innovative approach to software and systems reuse, (ii) formal mathematical methods for specification, design, and analysis of digital systems, and (iii) techniques and tools for integrating formal methods with existing methods, tools, and languages. The technology will provide a means by which there are no tradeoffs between COTS (commercial off the shelf) components and those required to satisfy the stringent reliability and safety requirements of safety-critical systems.

Potential Commercial Applications:
This is in the electronics design industry for both safety-critical and commercial systems. These products will be used by engineers within the computer, networking and semiconductor markets to develop reusable designs, reduce design cycle times and reduce time to market for electronic products and systems.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
1997
Phase II Amount
$587,501
___(NOTE: Note: no official Abstract exists of this Phase II projects. Abstract is modified by idi from relevant Phase I data. The specific Phase II work statement and objectives may differ)___ The development of verified reusable hardware specification components, manifest as synthesizable VHDL cores, represents a key technology that will enable engineering discipline to manage design complexity. The specific innovation we propose is the development of verified, synthesizable VHDL cores that include all the features, documentation, and support necessary to insure integration with customer designs with the high degree of reliability provided by the application of formal methods. The innovation is relevant to NASA as (i) an innovative approach to software and systems reuse, (ii) formal mathematical methods for specification, design, and analysis of digital systems, and (iii) techniques and tools for integrating formal methods with existing methods, tools, and languages. The technology will provide a means by which there are no tradeoffs between COTS (commercial off the shelf) components and those required to satisfy the stringent reliability and safety requirements of safety-critical systems.

Potential Commercial Applications:
This is in the electronics design industry for both safety-critical and commercial systems. These products will be used by engineers within the computer, networking and semiconductor markets to develop reusable designs, reduce design cycle times and reduce time to market for electronic products and systems.