SBIR-STTR Award

VLSI State Test Machine
Award last edited on: 12/19/2014

Sponsored Program
SBIR
Awarding Agency
NASA : JPL
Total Award Amount
$49,662
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Mark Acuff

Company Information

CADIC Inc

7874 SW Nimbus Avenue
Beaverton, OR 97008
   (503) 863-5201
   N/A
   N/A
Location: Single
Congr. District: 01
County: Washington

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1985
Phase I Amount
$49,662
The parameters achievable for a 96 pin state test machine has been defined. This machine can send and receive digital signals to/from all 96 pins, for the purpose of testing the functionality of an integrated circuit.The voltage levels are set (within specified limits) by the machine's controlling program, which is resident on a personal or mini computer. An unlimited number of test vectors can be used for extensive tests.Response time of the device under test is also be set (within specified limits) by the machine's controlling program.By building a test machine from gate arrays and a personal computer it should be possible to obtain the most cost effective functional tester yet built.STATUS: Phase I Only

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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