SBIR-STTR Award

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Optimal systolic architecture for the Navier-Stokes equations
Award last edited on: 3/7/02

Sponsored Program
SBIR
Awarding Agency
NASA : ARC
Total Award Amount
$381,123
Award Phase
2
Solicitation Topic Code
-----
Principal Investigator
Simon K Fok

Company Information

Zeroone Systems Inc (AKA: Technology Development of CA )

2431 Mission College Blvd.
Santa Clara , CA 95054
   N/A
   N/A
   N/A
Location: Single
Congr. District: 17
County: Santa Clara

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1984
Phase I Amount
$50,000
The objective is to construct a Systolic Navier-Stokes Attached Processor(SNAP) connected to a VAX computer for high speed NASA flow code computations. A high level architecture for the SNAP has been designed. The architecture consists of: (1) a narrow bandwidth linear solver which is currently under development for NASA by ZeroOne Systems, Inc. and (2) fast Fourier transform modules and matrix-vector multiplier modules which will be constructed using Sky Computers' Sky Warrior array processors. All these processors will be integrated with the host computer through the Apter DPS-2400 which is, in essence, a shared memory multiprocessor. The three NASA flow codes already studied will be mapped into the SNAP. This involves restructuring of the whole computational process in each code to facilitate systolic chaining; the actual computational algorithm will not be changed. Software will also be developed to coordinate the operations of multiple processors, shared memory and the host using low-level interprocessor communication primitives to create semaphores, critical regions and other synchronization primitives to ensure reliable operations of the SNAP. Cost-effectiveness of the SNAP with respect to a range of computers will be assessed.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
1986
Phase II Amount
$331,123
___(NOTE: Note: no official Abstract exists of this Phase II projects. Abstract is modified by idi from relevant Phase I data. The specific Phase II work statement and objectives may differ)___ The objective is to construct a Systolic Navier-Stokes Attached Processor(SNAP) connected to a VAX computer for high speed NASA flow code computations. A high level architecture for the SNAP has been designed. The architecture consists of: (1) a narrow bandwidth linear solver which is currently under development for NASA by ZeroOne Systems, Inc. and (2) fast Fourier transform modules and matrix-vector multiplier modules which will be constructed using Sky Computers' Sky Warrior array processors. All these processors will be integrated with the host computer through the Apter DPS-2400 which is, in essence, a shared memory multiprocessor. The three NASA flow codes already studied will be mapped into the SNAP. This involves restructuring of the whole computational process in each code to facilitate systolic chaining; the actual computational algorithm will not be changed. Software will also be developed to coordinate the operations of multiple processors, shared memory and the host using low-level interprocessor communication primitives to create semaphores, critical regions and other synchronization primitives to ensure reliable operations of the SNAP. Cost-effectiveness of the SNAP with respect to a range of computers will be assessed.