SBIR-STTR Award

The objective is to construct a Systolic Navier-Stokes Attached Processor(SNAP) connected to a VAX computer for high speed NASA flow code computations. A high level architecture for the SNAP has been designed. The architecture consists of: (1) a narrow bandwidth linear solver which is currently under development for NASA by ZeroOne Systems, Inc. and (2) fast Fourier transform modules and matrix-vector multiplier modules which will be constructed using Sky Computers' Sky Warrior array processors. All these processors will be integrated with the host computer through the Apter DPS-2400 which is, in essence, a shared memory multiprocessor. The three NASA flow codes already studied will be mapped into the SNAP. This involves restructuring of the whole computational process in each code to facilitate systolic chaining; the actual computational algorithm will not be changed. Software will also be developed to coordinate the operations of multiple processors, shared memory and the host using low-level interprocessor communication primitives to create semaphores, critical regions and other synchronization primitives to ensure reliable operations of the SNAP. Cost-effectiveness of the SNAP with respect to a range of computers will be assessed.

This research relates to the use of optimal systolic architectures for numerical solution of linear algebraic systems. Solution of structured linear algebraic systems is fundamental to most nasa flow codes, arising from applying finite differencing to partial differential equations such as the navier-stokes equations. The steps in this optimal design process are: (1) establishment of the basic principles of optimal systolic array system. (2) parallel development of a taxonomy for numerical linear algebra methods and the mapping of this taxonomy into corresponding systolic architectures. (3) optimizations of systolic configurations for each architecture.