In response to the proposal solicitation of ``Wideband Scalable Multi-channel Digital Receiver/Exciter (DREX)', this proposal presents a phase-I research plan committing to provide a set of study and experiment results, and conceptual design of a scalable coherence method. A new framework for wideband DREX with digitalized channel mismatch compensation is proposed. In the proposed architecture, digital signal processing relies on both a FPGA based real-time processor and a host PC with Graphic Processing Unit (GPU) for parallel computing. Major considerations in system design, measurement based modeling, channel mismatch compensation, as well as performance evaluation are discussed. Among many challenges are 1) to develop an effective system identification technique for the proposed channel model and 2) to develop a feasible channel mismatch compensation technique based on global optimization. Typical applications in wideband digital beamforming (DBF) and MIMO radar will be considered in developing and verifying the new schemes. Indeed, there are many questions and uncertainties associated with modeling and implementing the new schemes in real-time, which motivates us to study feasibility and implementation related issues using our lab facilities. This way, investigation results will be more convincing, which will pave the way for the phase II development.
Keywords: Multi-Channel, Digital Receiver/Exciter, Multiple-Input Multiple-Output Radar, Next Generation Radar, Wideband System, Digital Beam-Forming, Real-Time Implementation, Coherent
