SBIR-STTR Award

Modern space tracking and surveillance systems are being required to provide ever-increasing sensor resolution and real-time processing of image data. Existing rad-hard stream computing solutions are large, heavy, and require excessive power, and still do not meet the real-time computing throughput needed for modern image processing. There is a need to support missions using low-cost, rapid-deployment, configurable satellites. Intrinsix proposes to build a 300 krad(Si) rad-hard, heterogeneous, multicore System-on-Chip. Rad-Hard-by-Design techniques enable the design to be targeted for a high density process technology. The implementation will be a highly modular and scalable architecture consisting of several Digital Signal Processing cores and several General Purpose Processing cores. The cores will be interconnected with each other and with on-chip memories using a modern high-throughput Network-on-Chip technology. The SoC will be capable of running modern Real-Time Operating Systems, and will support high performance communications. The overall SoC is intended to support the Air Force Space Plug-and-Play Avionics architecture. In addition to supporting the needs of image processing, a design needs to support data processing requirements for a variety of other sensors, widening the available use cases within a space system.

Keywords:
Heterogeneous Processor, Rad-Hard, Soc, Dsp, Rhbd, Mhp, Stream Computing

Future space tracking and surveillance systems are being required to provide ever-increasing sensor resolution and real-time processing of image data. What is needed is a flexible, high performance monolithic computing engine which is rad-hard to 300 krad (Si) and an architecture which is suitable for stream computing on real-time imaging data. Completed Phase 1 tasks, presented a heterogenous multi-processor system-on-chip architecture and performance modeling results that demonstrated a design that addresses these advanced requirements of space based acquisision and tracking applications. Phase II efforts will create a high level SystemC/TLM based model of the architecture giving payload designers the ability to simulate specific image processing algorithims and system trade-offs (# of simutaneous targets tracked, image resolution, frame rate). Design configuation tools will also be developed to automate the configuration design and verification process, allowing for rapid delivery of customizable compute platforms. Industry standard GPP, DSP, and on-chip interconnect fabric standards will be targeted to an IBM 45nm SOI process. Process selection, rad-hard-by-design cell library and logic design techniques will be used to create an initial RTL SoC designs.

Keywords:
System on Chip SoC Heterogenous Stream Computing SystemC TLM RHBD Rad Hard by Design