Q-DOT proposes to develop an advanced RAMDAC for HWIL ladar scene generation. Future large-scale ladar scene generation requires advancements in algorithms and components to generate realistic ladar returns. Techniques and components for generating up to several hundred thousand instantaneous fields of view (IFOVs) with >70 dB dynamic range and 2 GHz instantaneous bandwidth (IBW) are needed. Digital signal processing can generate waveforms which are uploaded into very fast local memory (RAM) for scene generation. The digital-to-analog converter (DAC) and subsequent analog signal path must offer wide bandwidth and high resolution simultaneously. The proposed RAMDAC will combine deep (10k words) memory with a high-performance DAC (14 bits, 5 Gs/s) on a single chip. The proposed commercial SiGe BiCMOS technology offers >200 GHz HBTs and 0.12 micrometer CMOS, making it well suited for the RAMDAC. Its low cost and low power will enable the large scene generators required for MDA's HWIL simulators. The RAMDAC will be conceptually designed during Phase I. Prototype multichannel RAMDAC chips will be developed during Phase II. Phase III will result in cards using the RAMDAC chips interfaced to a HWIL ladar scene generator
