SBIR-STTR Award

Tessera Technologies will demonstrate the feasibility of applying stacked package and system-in-a-package designs to FPGA and RAM devices for single board systolic arrays for next generation missile defense. Working with Lockheed Martin, Tessera will develop a detailed system-in-a-package design for the FPGA and RAM combination properly configured for high density and functional connectivity to the systolic array architecture developed by Lockheed Martin. The design goal is to develop an array module design that achieves a 4X increase in density over current planar designs. Electrical, thermal and physical simulations will be used to optimize the design for high reliability and performance. Anticipated Benefits/Commercial Applications: It is common for applications that employ FPGAs to also require memory. There is growing interest from FPGA device suppliers and from electronics manufacturing suppliers for modular products that combine FPGA and memory. Full development of the FPGA plus memory module for this systolic array application will lay the groundwork for future standard product offerings able to penetrate military, medical, and communications markets. Compact FPGA plus RAM modules will find markets in image processing, sonar signal processing, portable ultrasound and other signal processing applications.

Keywords:
system-in-a-package, systolic array, 3D chip scale packaging, FPGA plus RAM, COTS based image processing, single board focal plane array, high performance density, stacked package

Increasing the density of seeker focal plane processing elements is critical to achieving multi-color, fine grained end-game target resolution and LADAR processing capabilities for missile interceptors. The objective of this research project is to continue development of new package stacking and interposer interconnect that allows 3-dimensional arrangement of programmable logic. This will result in a 4-fold increase in processing elements in a single seeker electronics board. In Phase I, feasibility of novel interconnect and stacking of Field Programmable Gate Array (FPGA) and Static Random Access Memory (SRAM) was demonstrated. Package stacking and the new array interconnect avoids the added weight, added signal latencies, signal integrity problems and reliability risks associated with the use of multiple boards and large connectors. Distributing signal routing to separate stacked interconnect elements reduces the complexity of any single element allowing these separate elements to be developed faster with higher yields and lower costs. Phase II will produce prototype hardware of the modular stacked package including the advanced distributed interconnect design developed in Phase I and testing of the hardware. Through a subcontract from Tessera, Lockheed Martin will provide schematic design support, test support and will contribute to the project the use of existing test facilities and hardware developed with Lockheed Martin resources.