In this project, INTRINSIC proposes to demonstrate production quality 3-inch semi-insulating SiC wafers based on the successful results obtained in the Phase I effort. The objectives of the Phase II project are to expand the ultrahigh purity (UHP) semi-insulating SiC wafer size from 2-inch to 3-inch with high yield, high crystal quality and reduced impurities. The wafers will be polished via INTRINSIC's proprietary chemical mechanical polishing (CMP) technique. Based on the successful proof of concept result obtained under the Phase I effort, the Company proposes to improve the manufacturing and the hardware areas for achieving a robust, high yielding 3-inch product line for Ballistic Missile Innovative Radar and RF applications. Design of experiments (DOE) approach will be used for 3-inch 6H semi-insulating growth process optimization. Development of chemical mechanical polishing (CMP) for 3-inch wafers will also be pursued since high quality surface finish is an essential parameter for achieving acceptable device characteristics. INTRINSIC will use a numerical model to simulate the thermal gradients and the radiation effects as a function of crystal growth process parameters. With this approach, a critical feedback to the DOE studies for fine process tuning will be obtained.
Keywords: silicon carbide, microwave materials, single crystal growth, insulating substrates, charge compensation, wafer manufacturing, purification, chemical m
