SBIR-STTR Award

Schottky Barrier CMOS for Space and Missile Applications
Award last edited on: 4/7/2006

Sponsored Program
SBIR
Awarding Agency
DOD : MDA
Total Award Amount
$849,981
Award Phase
2
Solicitation Topic Code
AF00-031
Principal Investigator
Glenn Carter

Company Information

Spinnaker Semiconductor

1325 American Boulevard E Suite 1A
Bloomington, MN 55425
   (952) 223-5250
   info@spinnakersemi.com
   www.spinnakersemi.com
Location: Multiple
Congr. District: 03
County: Hennepin

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2000
Phase I Amount
$99,981
Spinnaker Semiconductor will develop a low temperature variant of its proprietary Schottky Barrier CMOS (SBCMOS) technology. Cooled, short channel (<100nm) Schottky Barrier MOS devices offer the possibility for ballistic transport between source and drain and thus are expected to have tremendous performance advantages over their room temperature, conventional CMOS counterparts. These include the virtual elimination of gate oxide surface scattering and the resulting increase in carrier mobility, reduction in noise, and improved long-term reliability and/or switching performance. The SBCMOS technology is also unconditionally immune to parasitic bipolar effects such as latch-up and is orders of magnitude less sensitive to heavy-ion strikes and other single event phenomena. Furthermore, the process sequence is significantly simpler and more manufacturable than that for room temperature, conventional CMOS, while simultaneously offering more compact design rules for circuit layout and total dose hardness to 1Mrad. Finally, Spinnaker Semiconductor's SBCMOS process is an all-silicon technology that uses standard processing steps and is easily integrated into existing silicon fabrication lines, allowing it to achieve similar economies of scale compared to conventional silicon CMOS.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2003
Phase II Amount
$750,000
Spinnaker Semiconductor, in partnership with Lincoln Labs in Lexington, Massachusetts, will demonstrate 25nm physical gate length NMOS and PMOS devices based on Schottky source/drain technology. Spinnaker's patent-protected Schottky Barrier (SB) CMOS technology is a fundamental and strategic leap forward for the entire high-performance silicon CMOS manufacturing industry (>$150 Billion in 2000) and is easily ported to any existing advanced silicon CMOS factory. It will enable the volume production of ultra high performance silicon ICs three to four years and one to two technology generations ahead of current industry leaders. It is broadly applicable to any high performance logic application, as well as high frequency (Ethernet, RF, wireless) applications. It is scalable with relative ease into the sub-10 nm regime and has significant performance and manufacturability advantages over conventionally architected CMOS. It is naturally and inherently radiation-hard, as it is unconditionally immune to latch-up and other effects resulting from parasitic bipolar action.

Keywords:
latch-up, CMOS, schottky