Space Electronics, Inc. proposes to develop a low cost technique of utilizing commercially available application specific integrated 4 circuit (ASIC) foundries and commercial design tools to develop an advanced radiation hardened Digital Signal Processor (DSP). Such a technique could be used to develop other advanced IC functions at substantially lower costs than traditional radiation hardened IC f development programs. The technique consists of developing and capturing the IC design in a high level descriptive language (HDL) and performing functional and timing design simulation. The design will then be programmed into-a COTS Field Programmable Gate Array (FPGA) for design verification with commercially available software and hardware development tools and a hardware mod e . After verifi-cation, the design will be optimized and synthesized and then ported to a commercial CMOS epitaxial or silicon-on-insulator foundry because of their known high level of radiation tolerance. The high level design will be wafer foundry independent. Single Event Latchup (SEL) and Total Ionizing Dose (TID) radiation hardening will be accomplished through foundry/process/selection and IC design techniques. The selected design and process verification candidate is a 32-bit floating point digital signal processor, hardware and software compatible with Texas Instruments' TMS320C30 family. Successful demonstration of a low cost method for designing and fabricating complex digital radiation hardened ICs should greatly increase the availability of presently unavailable functions, such as 32-bit DSPs, 32- and 64-bit microprocessors, GPS receiver chip sets, etc. The availability of these functions will greatly enhance the technical capabilities of both military (GPS, SMTS, SBIRs, etc.) and commercial satellites systems.
Keywords: IC DESIGN, COTS, RAD-TOLERANT, RAD-HARD, FPGA, DSP, HDL
