General purpose computers used in the United States and other countries typically achieve lower performance than can be achieved with special purpose computers for a given application. This Phase I proposal addresses a relatively unexplored capability that has emerged in optical computing, which is the ability to completely reconfigure the gate-level interconnects of a digital computer on every clock cycle. The optical computing model used here makes use of arrays of optical logic gates interconnected in free space. Masks in the image planes block light at selected locations, thus customizing the gate-level interconnects. These masks need not be fixed, in fact they may be implemented with active logic gates, which offers the opportunity to completely reconfigure the gate-level interconnect on every clock cycle, although with a greater cost due to the increased number of active elements. Motivations for exploring this capability include fault tolerance, compact hardware realizations, remote reconfigurations, and better mappings from algorithms to architectures. The Phase I effort will explore the impact of gate-level reconfiguration on computer architecture, and the means for achieving a working prototype optical computer that exploits gate-level reconfiguration.
