SBIR-STTR Award

Algorithm-based fault tolerance (ABFT) is a new technique for detecting and correcting errors in a regular array of microprocessors. This technique enhances and complements conventional fault tolerance techniques and appears to offer considerable improvement in reliability at a modest cost. This approach is aimed specifically at processors designed to perform numerical computations for signal processing applications. The development of the ABFT technique is being continued and its applicability extended to a wider class of problems. The cost (in terms of hardware or computer time) of implementing the ABFT is being evaluated for various processing architectures and computational problems. The ABFT technique is a valuable technique for improving the reliability of multiprocessor systems, especially when implemented in VLSI/WSI technology. Applications are expected for both commercial and military parallel processing systems and for systolic arrays in particular.