SBIR-STTR Award

Lithography Cost Reduction for Rad Hard Integrated Circuits
Award last edited on: 10/27/2017

Sponsored Program
SBIR
Awarding Agency
DOD : DTRA
Total Award Amount
$149,999
Award Phase
1
Solicitation Topic Code
DTRA143-008
Principal Investigator
Thomas L Wolf

Company Information

Silicon Technologies Inc

4568 South Highland Drive Suite 300
Salt Lake City, UT 84117
Location: Single
Congr. District: 03
County: Salt Lake

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2016
Phase I Amount
$149,999
This program will combine Silicon Technologies analog automation technology ADONIS with EBDW technology. This combination will reduce design times and costs for Analog Trusted circuits and will facilitate reuse of obsolete, radiation-hardened, precision analog components. Originally funded by the DARPA GRATES program, ADONIS demonstrated that with analog specific modifications, ADONIS Straight Line technology that it was possible to extend the 1D approach to design analog circuits. EBDW has made significant advances in producing small geometry digital integrated circuits but little attention has been paid to using these techniques with analog circuits. Analog design is critical in the design of complex ICs. EBDW gridded design creates new floating elements, including inductors and antennas, which are not created by the designer, but are an artifact of the gridded design rules. ADONIS will give the designer the ability to control and model these elements during the design process. To shorten design times, companies REUSE design. Digital reuse is very efficient, but Analog reuse is inefficient requiring 80-90% of the original designs effort. ADONIS and EBDW will solve this problem. With EBDW and ADONIS, DoD programs will ensure that chips designed today will be portable to new technologies for the next 50 years.

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
----
Phase II Amount
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