Defense Electronics Corporation (DEC) proposes an innovative radiation hardened by design (RHBD) and reliability improvement solution for silicon, III-V compounds (e.g. SiGe, SiC, GaN, InP, GaAs,), carbon nanotubes (CNT), and graphene. The method is based on analyzing chip-partitioned quiescent current signatures associated with failure modes common to these process technologies. Furthermore, the method leverages unique process properties for a novel recovery architecture. Quiescent current and chip level integrated recovery (CLIR) satisfy defect detection and diagnosis, fault analysis and/or fault propagation, and recovery. This method is designed to work efficiently in a radiation environment, although it is designed to work equally well with process technologies exhibiting failure modes unrelated to radiation. This method is similar to Concurrent Error Detection (CED) but possesses very distinct differences. In addition, the CLIR technique can be configured to detect IDDQ current signatures related to total ionizing dose (TID) as well as single event upsets (SEU). Candidate architectures include analog, digital, mixed signal, high power and radio frequency (RF) designs. Built In Current Sensor (BICS) and CLIR techniques for a RHBD solution mitigate radiation effects in scaled processes using SiGe, SiC, GaN, InP, GaAs, carbon nanotubes, and graphene.
Keywords: Single-Event Effects, Single-Event Upset, Single-Event Transients, Total Ionizing Dose, Displacement Damage, Nano-Technology
