SBIR-STTR Award

Solutions for Single-Event Effects in Ultra Deep Submicron Semiconductor Technologies Using Simulation and Layout Techniques
Award last edited on: 10/23/2018

Sponsored Program
SBIR
Awarding Agency
DOD : DTRA
Total Award Amount
$1,099,074
Award Phase
2
Solicitation Topic Code
DTRA102-008
Principal Investigator
Klas Lilja

Company Information

Robust Chip Inc (AKA: RCI)

7901 Stoneridge Drive Suite 226
Pleasanton, CA 94588
   (925) 425-0823
   N/A
   www.robustchip.com
Location: Single
Congr. District: 15
County: Alameda

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2011
Phase I Amount
$99,264
Robust Chip (RCI) and Vanderbilt University (Vanderbilt) propose a joint project to create and characterize a comprehensive, accurate, single event simulation solution for ultra scaled (45nm, 32nm, and below) CMOS technologies. The project focus is on developing a production strength single event analysis solution for 45nm, 28nm and 22nm CMOS, building on the most advanced single event characterization software available. Additional work on layout implementation and novel layout methodologies, will guide the development of the software solution both for qualification and calibration purposes, and for guidance on and adaption to, important target applications. The key innovations behind the technology in this project, the layout technology LEAP, and the new simulation methodology in accuro, originate in earlier DTRA and DARPA sponsored projects.

Keywords:
Single-Event Effects, Single-Event Upset, Single-Event Transients, Total Ionizing Dose, Displacement Damage, Nano-Technology

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
2012
Phase II Amount
$999,810
This project offers two powerful and efficient solutions to solve the mounting problems in design of radiation hard electronics: • a range of ultra hard, high performance, sequential and combinatorial logic blocks based on the new, and enormously effective, LEAP RHBD layout methodology, and • an accurate and efficient analysis, design, and simulation solution for single events. The Layout design through Error Aware Positioning (LEAP) technique can reduce single event error rates by several orders of magnitude through rearrangements of the layout alone. The technique incurs minimal performance penalties. It requires no changes in the manufacturing process, and can therefore be applied for manufacturing in any standard semiconductor technology, which ensures cost effective manufacturing. The tremendous error rate reductions achievable by this technique have been verified experimentally in 180nm technology and in 28nm technology. The single event analysis and design software developed in this project is created by bringing together the advanced single event analysis tools from ISDE and RCI. This modeling solution allows for an accurate and predictive analysis of the effects of layout changes on single event behavior, something which is just not possible with other single event simulation techniques.

Keywords:
single event solution, RHBD, LEAP, SEU, SET, SEMU, error rate reduction, radhard design