SBIR-STTR Award

Robust Chip proposes to develop a unique, new technique to couple circuit simulation and numerical device simulation, for efficient, flexible, and accurate simulation of transient radiation effects at the circuit level. The technique provides the accuracy and flexibility of numerical device simulation for the mobile charge in a semiconductor substrate, combined with the accuracy and speed of compact model simulation for the circuit. It can provide detailed information about the interactions between the circuit, substrate, cell layout and spacing, for radiation effects. This information can be used both for the verification, optimization, and synthesis at the layout level, and also as input for accurate and appropriate models, and modeling techniques, at higher levels in the design hierarchy, as required for successful design automation. In phase 1 the simulation technique will be extended, completed, and implemented into a prototype simulation tool, and accuracy and speed of the method will be verified. Supporting the simulation technique, the generation of a suitable, specialized numerical mesh in the substrate, and the coupling between the mesh and the layout will also be addressed.

Keywords:
Simulation Of Transient Radiation Effects, Circuit And Substrate Simulation, Tcad, Radiation-Hardening-By-Design, Radhard Design Automation, Simulation Of Single Event Transie

The key innovation of the proposal is a novel, fast and accurate, algorithm (patent pending) to simulate substrate effects, in particular single event transients (SETs), in semiconductor circuits. This new method opens up a new capability for circuit designers to study a large set of substrate and layout related effects using simulation, helps them to make good choices regarding circuit design and layout, and greatly reduces the number of tests/experimental manufacturing lots required. In phase I we developed and demonstrated the novel simulation method. We showed that this method is as accurate as TCAD simulation at the device level, while being much faster (10-100X), and allowing the simulation of circuit response for circuits with 1000’s of transistors. In phase II we will develop this method into a production strength design tool, verify and calibrate simulation models by comparing to measurements, and use the method to investigate and develop novel radhard design concepts, built-in soft error resilience (BiSER), which reduce soft error rates in digital logic, with a minimum of area, power, and speed penalty.

Keywords:
Simulation Of Single Event Transients, Set Radhard, Design Techniques For Soft Error Protection Of Digital Logic, Robust Circuit Design, Coupled Mixed