SBIR-STTR Award

Replacing Bump Bonding with Self-Assembly of Supercooled Liquid Metal Microcapsules
Award last edited on: 1/14/2023

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$200,000
Award Phase
1
Solicitation Topic Code
C54-33b
Principal Investigator
Ian Tevis

Company Information

Safi-Tech Inc

1575 Food Sciences Building
Ames, IL 50011
   (815) 326-2902
   N/A
   www.safi-tech.com
Location: Single
Congr. District: 04
County: Story

Phase I

Contract Number: DE-SC0022772
Start Date: 6/27/2022    Completed: 2/26/2023
Phase I year
2022
Phase I Amount
$200,000
This proposal addresses the widespread problem of dead zones and reliability in large format circuit assembly. This problem is caused by the high soldering temperature needed to make high-density interconnects in thin semiconductor chips using flip chip solder bump bonding technology. The size scales for the solder interconnects are not accessible via traditional low-cost solder printing or ball mounting but with a lengthy and costly bump bonding process to produce the small and precise solder bumps. Highly sensitive sensor pixels and high-density interconnects between readout and sensor chips are necessary for the continued advancement in medical and scientific instruments, but also of high energy physics and upgrades to facilities such as those at the Department of Energy and others. Large format chips have challenges forming and or keeping the flip chip interconnects joined at the device edge because of coefficient of thermal expansion mismatch causing dynamic warpage during the high temperature soldering process. The problem of the high heat needed for soldering and the problem of precise placement of solder bumps is being addressed in this proposal by using solder metal microcapsules in a supercooled liquid state that are placed via a self-assembly process. The supercooled liquid state allows the application of liquid metal solder at temperatures dramatically lower than normal solder reflow temperatures. The objective of the multiphase project is to replace bumps on a readout application-specific integrated circuit (ASIC) with a supercooled liquid metal microcapsule precisely placed via a simple and cost-effective self-assembly process. The supercooled liquid nature of the microcapsules will then enable solder reflow of a higher melting alloy, composed of SnAgCu, at lower temperatures than traditionally needed (=130 vs. peak reflow 250 °C) with high interconnect density and low edge defects. The Phase I work plan covers the tailoring of previously developed supercooled liquid microcapsules of SnAgCu to the proposed self-assembly process by means of chemical surface coatings. These specialized microcapsules will be self-assembled into high density arrays on test vehicles designed to mimic the thickness, feature size, and interconnect density of readout and sensor chips. The test vehicles will then be interconnected at temperatures =130 °C and inspected for their quality and relevance to commercial and government interests. The resulting interconnect will perform comparably to SnAgCu in solder joint quality and better in interconnect yield at the die edge and cryogenic reliability because of the lower reflow temperature. The Phase II project will go on to use actual readout and sensor chips with full interconnect and function characterization. The defects and damage caused by coefficient of thermal expansion mismatch are problematic not only in the flip chip bonding process for high energy physics but in advanced packaging in all aspects of electronics manufacturing. Electronics manufacturers in consumer electronics, automotive, medical technology, and other sectors are facing commercial market demands to develop products that are thinner, flexible, lighter weight, or have higher-density miniaturization with increased functionality. The self-assembly process of supercooled liquid metal microcapsules proven out in the Phase I and then advanced to commercial readiness in a Phase II will allow these industries to meet this demand with new designs and materials that are otherwise unsuitable for high-heat interconnect processes, while at the same time improving operating efficiency by forming interconnects 3X to 15X faster than current methods and reducing associated operating energy costs by up to 70%.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
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