SBIR-STTR Award

High-Channel Count Electronic Tools for Picosecond (ps) Timing
Award last edited on: 1/14/2023

Sponsored Program
STTR
Awarding Agency
DOE
Total Award Amount
$199,944
Award Phase
1
Solicitation Topic Code
C54-33e
Principal Investigator
Phaneendra Bikkina

Company Information

Alphacore Inc

304 South Rockford Drive
Tempe, AZ 85281
   (480) 494-5618
   info@alphacoreinc.com
   www.alphacoreinc.com

Research Institution

University of Houston

Phase I

Contract Number: DE-SC0022902
Start Date: 6/27/2022    Completed: 6/26/2023
Phase I year
2022
Phase I Amount
$199,944
The DOE Office of High Energy Physics (HEP) has called for the research of amplifying, digitizing, and multiplexing circuits suitable for numerous emerging ultra-low background detector and sensor components, including specialized detectors planned for HEP and Nuclear Physics (NP) experiments. Timing information is a critical tool in background reduction techniques in these experiments. Stable reference clocks, without suffering from drifting phase delays, must be synchronized to those components which could be distributed over distances of the order ten to twenty meters. Future experiments will require 4D or 5D detectors capable of time resolution in the picosecond range or better over channel counts that may exceed 100,000. Typical circuit blocks for precision timing generation such as Phase-Locked Loops (PLL), Delay-Locked Loops (DLL), Timing Discriminators and Time to Digital Converters (TDCs), that operate with radiation hardness (RH), and ultralow power in extreme environments, are needed as recognized in a recent DOE HEP strategic report. General statement of how this problem is being addressed. For this critical distributed clock need, Alphacore will develop a radiation-hard (RH) Phase Synchronization and Jitter Cleaning System (PSJC) based PLL for clock generation and distribution using an Application Specific Integrated Circuit (ASIC) device with on-chip ultralow power picosecond measurement, including very low added jitter from an integrated high accuracy phase noise and jitter measurement module. The SWaP PSJC will be implemented in a CMOS process (the same process CERN is using to make most of the circuits for HL-LHC), and the goal is to meet the stringent TID requirements of the HL-LHC (and other DOE HEP experiments). What is to be done in Phase I Alphacore will demonstrate the feasibility of the PSJC ASIC concept during Phase I, followed by fabrication and testing (including radiation tests) of a prototype in Phase II. Note that Alphacore successfully finished a DOE SBIR (HEP) Ph1 study on this subject in the spring of 2019 and has continued to develop this challenging technology using IRAD funding, making significant progress since then. This reduces the risk of the proposed effort considerably. Commercial Applications and Other Benefits (limited to the space provided). The design significantly improves state-of-the-art of power dissipation, component size and RH of comparable designs. The design is significantly more cost-effective than comparable designs. All these benefits are critical for the LHC luminosity upgrades. Dr. Roger Rusack, from CERN, stated no other group is currently performing R&D in RH ASIC design for sub picosecond rate for HL-LHC and this work is thus truly unique. Benefits to the public: The high luminosity upgrades of LHC at CERN require the employment of hundreds of thousands of readout channels. Detector data volumes at the HL- LHC will be ~100 times more than today. COTS data transmission solutions cannot be used in HL-LHC for two main reasons: they will not function in a high radiation environment, and they are in general too massive to be placed inside detectors, where added mass degrades the measurements being made. Synchronization in sub picosecond range is required. These components will likely need to be custom-designed since COTS components very rarely meet RH and density requirements of these applications. Since the PSJC improves quality of critical electronics needed at HL-LHC and has cost advantages compared to other available solutions, it provides significant benefits to the public. The developed RH PSJC can be used in space applications by NASA and ESA, and in DoD space and strategic applications for internal satellite communication networks. Alphacore has already been presenting this technology to numerous companies and several of them provided a support letter for our proposal (BNL. ORNL, UofArizona, UC-Santa Cruz). In addition, during his recent visit to Alphacore, a senior director from a CMOS foundry stated that the most sought-after IP block by their defense customers is a rad-hard 6-12GHz PLL. This indicates that there is already a good market for the hardened components resulting from this work. As listed in this section the fields of research and markets that can assume great benefits from the proposed technology are large and have a need for large quantities of the proposed products. Thus, it will not be difficult for the Alphacore team to obtain further funding, in addition to the SBIR funding, for this development. Our plan is to start the rigorous effort of finding commercial funding already in Phase I. Note that Alphacore was just recently able to find significant external funding commitments from interested commercialization partners (one of which is a >$8B market cap company) for two DOE Nuclear Physics SBIR Phase II proposals ($600k and $500k, respectively). Alphacore thus has the capability finding extra funding to help commercialize p

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
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