SBIR-STTR Award

Automated Calibration, characterization and optimization of near term quantum processors.
Award last edited on: 9/5/22

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$230,000
Award Phase
1
Solicitation Topic Code
C53-06a
Principal Investigator
Yuval Baum

Company Information

Q-CTRL Federal LLC

555 West 5th Street Floor 35
Los Angeles, CA 90013
   (720) 260-4667
   N/A
   N/A
Location: Single
Congr. District: 34
County: Los Angeles

Phase I

Contract Number: DE-SC0022467
Start Date: 2/14/22    Completed: 2/13/23
Phase I year
2022
Phase I Amount
$230,000
Q-CTRL Federal, LLC, with assistance from our Partners at Sandia National Laboratory, will develop software for pulse level quantum control, automated calibration, and characterization for the improvement of near-term gate-model quantum computers. The result will be an AI-based toolset compatible with any quantum hardware system that can deliver up to 10X performance gains, >10X improvements in the usable calibration window, and up to 100X improvements in hardware-tuneup efficiency relative to existing scripted approaches (wall-clock time and number of measurements required). These software tools will include fully autonomous and device sensitive procedures that may be used both by hardware research and development teams as well as external users of cloud-accessible quantum computers. This project will focus on building an autonomous package that is able to design, calibrate, and recalibrate the key parameters used in defining quantum logic operations across entire multiqubit quantum devices. By leveraging AI tools that interact directly with hardware, there is no need for human intervention; the agent determines the relevant parameters needed to realize high performance quantum hardware, resilient against slow parameter changes (drifts) and able to dramatically improve overall system functionality. Our project will build on Q-CTRL’s early research developing autonomous AI agents for quantum logic gate design and calibration. These techniques have been validated on real cloud quantum computing hardware to deliver over 2X performance gains in multiqubit gate fidelity and up to 25+ days of robust operation without the need for recalibration. We will leverage the QSCOUT quantum testbed at Sandia for development and testing purposes and build upon Sandia’s work developing pyGSTi for quantum gate characterization. To complement the automated optimization procedures, Q-CTRL will develop software tools for multi-qubit device validation. The main challenges with the current, frequently used, validation methods are their poor scaling with the number of qubits and their inability to account for contextual and realistic coherent errors. The gap between popular existing measures and real hardware performance at the algorithmic level was recently highlighted in work by the Sandia team. We will develop a reliable measure capable of capturing relevant noise dynamics in complex systems without ion to the point of reducing predictive utility. The team at Q-CTRL includes experts in modern machine learning tools applied to physical systems, optimal control theory, and quantum physics. This expertise includes direct experimental experience with both superconducting and cold atom devices and is translated to useful tools through an experienced team of software developers. Sandia has deep expertise in the characterization of complex quantum systems and the operation of cloud-accessible trapped-ion quantum computers. During Phase I, Q-CTRL will (1) develop automation software tools and integrate them with pyGSTi to achieve the hardware-performance advantages described above; and (2) develop software tools for multi-qubit devices characterization and validation with input from the Sandia team. A successful completion of phase I is an essential step towards full algorithm-level optimization which aims to deliver the first useful quantum machines for industry-relevant applications. Phase I further establishes a clear pathway to extension of our work in Phase II, with a focus on hardware integration into testbeds, and extension of AI-based hardware optimization approaches to the circuit-compilation lev

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
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