SBIR-STTR Award

Densely packed gamma-ray imaging and spectroscopy instruments employ high performance multichannel electronics which occupy large volume and dissipate excessive heat- Therefore, a low power application specific integrated circuit (ASIC) incorporating multiple channels of digitizers and post processing electronics is of critical importance for nuclear physics (NP) instrumentation- Microchip Corp- proposes to develop an ASIC with a novel 12-bit 32 channel 200MSps ADC to provide digital peak detection capabilities for multichannel radiation detector systems- The ASIC will accept random pulse data on 32 input channels producing a single digital output per channel having peak amplitude, timing, and channel address information- This ASIC will offer high channel density and low power consumption that cannot be achieved in systems based on off-the-shelf components- The integrated 32-channel ADC will be able to operate in two modes- In the first mode of operation, the ASIC will support applications in detector instruments- To increase the commercialization potential, the ASIC will also support a second mode of operation when the ADC data is directly supplied to the serial outputs through the JESD204B standard compliant interface-

Densely packed gamma-ray imaging and spectroscopy instruments employ high performance multichannel electronics which occupy large volume and dissipate excessive heat. Therefore, a low power application specific integrated circuit (ASIC) incorporating multiple channels of digitizers and post processing electronics is of critical importance for nuclear physics (NP) instrumentation. Microchip Corp. proposes to develop an ASIC with a novel 12-bit 32 channel 200MSps ADC to provide digital peak detection capabilities for multichannel radiation detector systems. The ASIC will accept random pulse data on 32 independent input channels producing a single digital output having peak amplitude, timing, and channel address information. This ASIC will offer high channel density and low power consumption that cannot be achieved in systems based on off-the-shelf components. The integrated 32-channel ADC will be able to operate in two modes. In the first mode of operation, the ASIC will support applications in detector instruments. To increase the commercialization potential, the ASIC will also support a second mode of operation when the ADC data is directly supplied to the serial outputs through the JESD204B standard compliant interface. In Phase I, the ASIC’s architecture was developed and modeled, the critical circuits were designed, and the proof of feasibility based on simulations was provided. Phase II will result in the fabricated and tested ASIC’s prototype ready for commercialization in Phase III. Commercial applications and other

Benefits:
According to the latest market study released by Markets and Markets, the global data converter market is expected to reach $5.08B by 2023, growing at a CAGR of 6.3%. This projection confirms the great potential for the proposed ASIC. There are no 32-channel 12-bit ADC sampling at 200MSps rate available on the market. The status of market lead in providing the multichannel ADC will contribute to the success of our product. The ASIC will satisfy the most demanding energy and timing measurement requirements in a variety of multichannel detectors being developed by NP communities. In addition, the proposed ASIC will be applicable for multichannel signal processing in wireless communication systems and synthetic aperture radars. The ASIC will be provided as a component, and the ADC array will be also provided as an IP block.