Next generation experiments in High Energy Physics require the use of thinned detectors with high density interconnects; however, present manufacturing techniques for wafer thinning produce very low yields. Standard processing techniques have proven to be unacceptable for the production of high pixel count detector assemblies. Therefore, this project will develop technology for plasma-etch-based wafer thinning, along with new manufacturing techniques for the production of high density flip chip interconnects. In Phase I, high density solder bumps, compatible with 50 micron pixilated detector arrays, will be fabricated on six-inch silicon wafers. The wafers will be thinned to 100 microns, using plasma etch processing, and subsequently diced into chips suitable for detector integration.
Commercial Applications and Other Benefits as described by the awardee: There are growing niche markets for fine-pitch wafer bumping for devices with I/O pitches of 100µm and less. In addition to the High Energy Physics application, medical imaging is another area where pixilated detectors are being utilized. In these applications, the size of the pixels is typically 50µm to 100µm in the smallest dimension, and the associated wafer bumping, handling, and assembly of these devices becomes considerably more difficult compared with most commercial applications
