SBIR-STTR Award

An intelligent small computer system interface for FASTBUS
Award last edited on: 2/20/02

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$521,954
Award Phase
2
Solicitation Topic Code
-----

Principal Investigator
Charles J Hubbard

Company Information

Jorway Corporation

623 New York Avenue
Huntington, NY 11743
   (631) 351-1203
   sales@jorway.com
   www.jorway.com
Location: Single
Congr. District: 03
County: Suffolk

Phase I

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1990
Phase I Amount
$50,000
In this project, an intelligent interface between FASTBUSand the American National Standards Institute standard small computer system interface (SCSI) bus will be investigated. Phase I's objective is to develop a detailed hardware design of such aninterface and to perform an analysis of the software required torelieve FASTBUS programmers of any SCSI responsibility. The proposed interface will implement the SCSI wide data transferoption, providing a 32-bit-wide data path. A transfer rate of 40 Mbytes per will be possible, using the synchronous protocol and tin-dng specified in the SCSI The interface will @on as a FASTBUS master or slave, and as either an SCSI initiator or target. As an initiator, it will permit any other FASTBUS master to access any SCSI peripheral oranother processor acting as an SCSI processor " device. The interfacewill also be programmed to respond as an SCSI target of the processor, permitting a host computer to initiate communicationwith any FASTBUS device. A FASTBUS device will be able tointerrupt another processor @ device on the SCSI bus, and an SCSI will be able to access any FASTBUS interrupt service device. Creation of the wide data path is planned, using a parallel array of commercially available SCSI protocol chips,suitably synchronized. An on-board microprocessor will perform lowlevel control of the chips selected. At a higher level, it willimplement all mandatory SCSI messages and commands, plus thecommands specified for a variety of SCSI devices that might be used with FASTBUS. Anticipated Results/Potential Commercial Applications as described by the awardee:The planned FASTBUS module will provide a highspeed communication link between FASTBUS and a variety of computersand workstations. Many of these provide the SCSI port at noadditional cost, and in some cases, SCSI is the only possiblecommunication medium. In addition, the planned interface willallow any of a wide range of SCSI peripheral devices to be used with FASTBUS with no additional hardware. A connection betweenFASTBUS and computer automated measurement and control (CAMAC) ispossible using recently developed SCSI CAMAC crate controllem

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
1991
Phase II Amount
$471,954
The design of a FASTBUS module providing an intelligent interface to the American National Standards Institute standard small computer system interface bus (SCSI) was investigated in Phase I. The module is to provide a high speed communication link between a FASTBUS system and a variety of computers and workstations. It will also allow any SCSI peripheral device, such as a disk or tape drive, to be directly connected to a FASTBUS system. The result of Phase I was the design of a module providing either four independent eight-bit wide SCSI ports, or a single thirty two-bit wide port implementing the SCSI wide data transfer option. In the latter case, a transfer rate of twenty megabytes per second will be possible, using the SCSI synchronous protocol. The interface will function as either an SCSI bus initiator or target. As an initiator, it will permit any FASTBUSmaster to access any SCSI peripheral, or another processor responding as an SCSI processor type device on the SCSI bus. When acting as a target, the module will respond as a processor type device itself, and permit another SCSI initiator to exchange data with FASTBUS slaves or memory. To achieve this functionality, the module will have the capability of acting as a FAS1 BUS master as well as a slave. Phase I resulted in a proposed design of the software interface to the modules as well as a hardware proposal. The latter uses individual microcontrollers to control several SCSI protocol chips, and a microprocessor to provide overall supervision and communication with the FASTBUS segment via a FASTBUS protocol chipset. During Phase II, the hardware design will be breadboarded, and the software written for each of the microprocessor systems. The objective will be a fully functional FASTBUS module, which will be tested in several actual FASTBUS environments.Anticipated Results/Potential commercial Applications as described by the awardee:The proposed FASTBUS module will provide a high speed communication link between FASTBUS and a variety of computers and workstations. Many of these provide the SCSI port at no additional cost, and in some cases SCSI is theonly possible communication medium. In addition, the proposed interface will allow any of a wide range of SCSI peripheral devices to be used with FASTBUS with no additionalhardware. A connection between FASTBUS and computer automated measurement and control (CAMAC) is possible using recently developed SCSI CAMAC crate controllers.