Phase II year
2022
(last award dollars: 1685450826)
Phase II Amount
$1,099,638
Development of high voltage gated semiconductor device process that leverages the enhanced power handling capability of SiC, and remediates the undesirable effects (threshold voltage instability, increased interface capacitance) associated with native SiO2 growth from commercially available 4H-SiC and 6H-SiC polytypes. The process improvement and resultant performance enhancements gained will be validated by characterization of prototype devices
