Phase II year
2017
(last award dollars: 2019)
Phase II Amount
$2,000,000
In this seed effort, we will utilize our existing CMOS integrated power inductor process to develop a custom IPD that includes an array of power inductors designed to face-to-face bond with a reference digital-polar power amplifier design exploiting both GaN and CMOS. Building on an existing hybrid GaN/CMOS digital-polar power amplifier (PA) design, a custom CMOS chip will be designed to enable the integration of both the power inductor IPD and a chiplet containing the required GaN devices through face-to-face bonding. The assembled module will leverage the high inductance density, saturation current and inductance-to-resistance ratio of Ferrics power inductor process with the low on resistance and gate capacitance available with GaN power FETs. The work conducted during this study will demonstrate the value of integrated devices based upon magnetic thin-films and justify process development and technology transfer for the monolithic integration of magnetic thin-films with GaN.
